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Title:FPGA Blog - field programmable gate array
Description:FPGA (field programmable gate array) and structured ASIC information
Keywords:fpga, structured asic, field programmable gate array, programmable logic devices, plds, cplds, complex programmable logic devices, fpgas
Body:
FPGA Blog - field programmable gate array
FPGA Blog - field programmable gate array and structured asic
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Recent Posts
Xilinx Spartan-6 FPGA FamilyPosted by Ken Cheung in FPGA on Monday, February 2, 2009
The Xilinx Spartan-6 FPGA Family is built for connectivity and low power. The Spartan-6 devices enable system developers to meet demand for new features, while at the same time reducing system costs by up to half for lower power, greener products. Spartan-6 devices are sampling now. The Spartan-6 FPGA family is fabricated on a low-power 45nm, 9-metal layer, dual-oxide process technology. The new family delivers an optimal balance of low risk, low cost, low power, and high performance. The Spartan-6 FPGA family #8217;s efficient, dual-register 6-input LUT (look-up table) logic structure leverages the Virtex architecture to enable cross-platform compatibility and to optimize system performance.
Continue reading raquo;
Xilinx Virtex-6 FPGA DevicesPosted by Ken Cheung in FPGA on Monday, February 2, 2009
Xilinx #8217;s new Virtex-6 FPGA Family features 50% lower power and 20% lower cost than previous generations. The Virtex-6 FPGA family is built on a 40nm process using third-generation Xilinx ASMBL architecture. Providing 15% higher performance and 15% lower power consumption compared to competitive 40nm FPGA offerings, the new devices operate on a 1.0v core voltage with a 0.9v low-power option. This enables system architects to integrate Virtex-6 FPGAs into their designs to enable #8216;green #8217; central offices and data centers. Initial Virtex-6 device samples will be available in the second quarter of 2009. Xilinx targeted design platforms providing fully integrated software support, tested IP, and reference designs with boards and kits will be available in the second half 2009.
Continue reading raquo;
Altera Stratix IV GT and Arria II GX FPGA FamiliesPosted by Ken Cheung in FPGA on Monday, February 2, 2009
Altera introduced their new Stratix IV GT and Arria II GX 40-nm FPGA families. The Arria II GX and Stratix IV GT utilize common transceiver technology and are supported by a common set of development tools that enable system designers to develop full system-on-chip (SoC) solutions. This portfolio delivers both FPGA solutions from 16K logic elements (LEs) to 530K LEs, and HardCopy ASIC solutions of up to 11.5 million ASIC gates. Stratix IV GT devices are shipping now. The first Arria II GX device, the EP2AGX125, will ship in May 2009 with production devices scheduled for the fourth quarter of 2009. Budgetary pricing for the smallest device, the EP2AGX20, will start as low as $15 for 100K unit quantities in 2010.
Continue reading raquo;
Altera Quartus II Software Version 9.0Posted by Ken Cheung in Tool on Monday, February 2, 2009
Altera launched version 9.0 of their Quartus II software for CPLD, FPGA, and HardCopy ASIC development. Version 9.0 supports Altera #8217;s new Stratix IV GT and Arria II GX FPGAs. Altera will separately offer the ModelSim Altera Edition, which was previously available only through a full Quartus II software subscription. The ModelSim Altera Edition delivers to users 33% faster simulation speeds compared to the ModelSim Altera Starter Edition, with no restrictions in design size. A beta version of the Quartus II software version 9.0 is available now. In March, Altera will release the 9.0 production version of Quartus II software, the ModelSim Altera Edition, and the ModelSim Altera Starter Edition. ModelSim Altera Edition will be available for $945 per seat. Quartus II software subscribers receive the ModelSim Altera Starter Edition and a full license to the IP Base Suite, which includes 11 of Altera #8217;s most popular IP (DSP and memory) cores. The annual software subscription is $2,495 for a node-locked PC license.
Continue reading raquo;
Altera to Make Five Presentations at DesignConPosted by Ken Cheung in Event on Monday, February 2, 2009
Altera will be attending DesignCon, February 4-5, at the Santa Clara Convention Center. Altera will make five presentations:
Design/Verification for High-Speed I/Os at Multiple to gt;10 Gbps
FPGA/ASIC Pre-Driver PDN SSN and Its Impact on SSJ
Incorporating SSN Analysis in Constraint-Based System Design
A New Physical Mechanism-Based Jitter Classification Method
Continuous PLL Adaptation to Variable Reference Input Frequency
Continue reading raquo;
laquo; Previous Posts
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Ethernet Direct Rolls Out IRE-323EC Industrial Ethernet Switch Fri, 06 Feb 2009 22:40:21Gleichmann Electronics Research Introduces SEmulator Interface Box Fri, 06 Feb 2009 22:36:39Molex HSAutoLink Fully Supports 1394 Copper Automotive Specification Fri, 06 Feb 2009 22:20:56TDK-Lambda Announces LS Series 25W, 35W Models Power Supplies Fri, 06 Feb 2009 22:10:08Gil Automations Joins MatrikonOPC Integrator Partner Program Fri, 06 Feb 2009 00:17:08
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